The use of porous low k dielectric materials for Dual Damascene patterning in microelectronic devices requires much higher selectivity for removal of organic sacrificial fill material and etched or un-etched photo resist during cleaning, while preventing attack (undercut) of the porous low k interlayer dielectric (ILD) material. In addition, transitioning from a wet cleaning platform utilizing batch processing to a single wafer process requires reduction of etching times from about 10 minutes to about 1 min. Cleaning must be accomplished with no degradation of the dielectric constant and with no damage to metal (such as copper, titanium or tungsten) portions, of the Damascene structure.